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4-mbit (128k x 36) pipelined sync sram cy7c1347f cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05213 rev. *d revised april 9, 2004 features ? fully registered inputs and outputs for pipelined oper- ation ? 128k by 36 common i/o architecture ? 3.3v core power supply ? 2.5v/3.3v i/o operation ? fast clock-to-output times ? 2.6 ns (for 250-mhz device) ? 2.6 ns (for 225-mhz device) ? 2.8 ns (for 200-mhz device) ? 3.5 ns (for 166-mhz device) ? 4.0 ns (for 133-mhz device) ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed writes ? asynchronous output enable ? jedec-standard 100-pin tqfp, 119-pin bga and 165-pin fbga packages ? ?zz? sleep mode option and stop clock option ? available in industrial and commercial temperature ranges functional description [1] the cy7c1347f is a 3.3v, 128k by 36 synchronous-pipelined sram designed to support zero-wait-state secondary cache with minimal glue logic. cy7c1347f i/o pins can operate at either the 2.5v or the 3.3v level, the i/o pins are 3.3v tolerant when v ddq = 2.5v. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise is 2.6 ns (250-mhz device) cy7c1347f supports either t he interleaved burst sequence used by the intel pentium proc essor or a linear burst sequence used by processors such as the powerpc ? . the burst sequence is selected through the mode pin. accesses can be initiated by asserting either the address strobe from processor (adsp ) or the address strobe from controller (adsc ) at clock rise. address advancement through the burst sequence is controlled by the adv input. a 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qual ified with the four byte write select (bw [a:d] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are conducted with on-chip sy nchronous self-timed write circuitry. three synchronous ch ip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output three-state control. in order to provide proper data during depth expansion, oe is masked during the first clock of a read cycle when emerging from a deselected state. note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. logic block diagram address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a 0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register dq d , dqp d byte write register dq a , dqp a byte write driver dq b , dqp b byte write driver dq c , dqp c byte write driver dq d ,dqp d byte write driver
cy7c1347f document #: 38-05213 rev. *d page 2 of 19 selection guide -250 -225 -200 -166 -133 unit maximum access time 2.6 2.6 2.8 3.5 4.0 ns maximum operating current 325 290 265 240 225 ma maximum cmos standby current 40 40 40 40 40 ma shaded areas contain advance information. pl ease contact your local cypress sales re presentative for availability of these part s. pin configurations a a a a a 1 a 0 nc nc v ss v dd nc nc a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode byte a byte b byte d byte c 100-pin tqfp cy7c1347f
cy7c1347f document #: 38-05213 rev. *d page 3 of 19 pin configurations (continued) 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc nc dqp c dq c dq d dq c dq d aa aa adsp v ddq ce 2 a dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc nc nc nc nc nc nc nc v ddq v ddq v ddq aaa a ce 3 a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc bwe bw d zz 119-ball bga a 165-ball fbga 234 567 1 a b c d e f g h j k l m n p r nc nc nc dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc nc v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc nc v ss nc a a dq c v ss dq c v ss dq c dq c v ss v ss v ss v ss v ss v ss v ss a1 dq d dq d nc nc v ddq v ss nc 891011 nc adv a adsc nc oe adsp a nc v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss
cy7c1347f document #: 38-05213 rev. *d page 4 of 19 pin definitions name (bga,fbga) name (100tqfp) i/o description a 0, a 1, a a [16:0] input- synchronous address inputs used to select one of the 128k address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a [1:0] feeds the 2-bit counter. bw a, bw b, bw c, bw d bw [a:d] input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all by tes are written, regardless of the values on bw [a:d] and bwe ). bwe bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk clk input-clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselec t the device. adsp is ignored if ce 1 is high. ce 2 ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are three-stated, and act as input data pins. oe is masked during the first clock of a read cycle when emerging from a deselected state. adv adv input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automatically increments the address in a burst cycle. adsp adsp input- synchronous address strobe from processor, sampled on the rising edge of clk . when asserted low, addresses presented to th e device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc adsc input- synchronous address strobe from controller, sampled on the rising edge of clk . when asserted low, addresses presented to th e device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz zz input- asynchronous zz ?sleep? input . this active high input places the device in a non-time-critical ?sleep? condition with data integrity pres erved. for normal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dq a, dq b dq c, dq d dqp a, dqp b, dqp c, dqp d dqs dqps i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by t he addresses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqps are placed in a three-state condition. v dd v dd power supply power supply inputs to the core of the device . v ss v ss ground ground for the co re of the device . v ddq v ddq i/o power supply power supply for the i/o circuitry . v ssq v ssq i/o ground ground for the i/o circuitry . mode mode input- static selects burst order . when tied to gnd selects linear burst sequence. when tied to v ddq or left floating selects interleaved bur st sequence. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. nc nc no connects .
cy7c1347f document #: 38-05213 rev. *d page 5 of 19 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t co ) is 2.6 ns (250-mhz device). the cy7c1347f supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the linear burst sequence is suited for processors that utilize a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the ad dress strobe from processor (adsp ) or the address strobe from controller (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the firs t address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw [a:d] ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output thr ee-state control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at cloc k rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a [16:0] ) is stored into the address advancement logic and the address register while being presented to the memory core. the corre- sponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 2.6 ns (250-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. once the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output will three-state immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a [16:0] is loaded into the address register and the address advancement logic while being delivered to the ram core. the write signals (gw , bwe , and bw [a:d] ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on the second clock rise, the data presented to the dqs and dq ps inputs is written into the corresponding address location in the ram core. if gw is high, then the write operation is controlled by bwe and bw [a:d] signals. the cy7c1347f provides byte write capability that is described in the write cycle description table. asserting the byte write enable input (bwe ) with the selected byte write (bw [a:d] ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self -timed write mechanism has been provided to simplify the write operations. because the cy7c1347f is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs and dqps inputs. doing so will three-state the output drivers. as a safety precaution, dqs and dqps are automatically three-stated whene ver a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc adsc write accesses are initiated when the following condi- tions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw [a:d] ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses require a single clock cycle to comple te. the address presented to a [16:0] is loaded into the address register and the address advancement logic while being delivered to the ram core. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs and dqps is written into the corresponding address location in the ram core. if a byte write is conducted, only the selected bytes are written. bytes not selected during a byte write operation will remain unaltered. a synchronous self -timed write mechanism has been provided to simplify the write operations. because the cy7c1347f is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs and dqps inputs. doing so will three-state the output drivers. as a safety precaution, dqs and dqps are automatically three-stated whene ver a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1347f provides a two-bit wraparound counter, fed by a [1:0] , that implements either an interleaved or linear burst sequence. the interleaved burs t sequence is designed specif- ically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user-selectable through the mode input. asserting adv low at clock rise will automatically increment the burst counter to the next address in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low.
cy7c1347f document #: 38-05213 rev. *d page 6 of 19 interleaved burst sequence first address second address third address fourth address a [1:0] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst sequence first address second address third address fourth address a [1:0] a [1:0] a [1:0] a [1:0] 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz snooze mode standby current zz > v dd ? 0.2v 40 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to snooze current this parameter is sampled 2t cyc ns t rzzi zz inactive to exit snooze cu rrent this parameter is sampled 0 ns truth table [2, 3, 4, 5, 6] next cycle add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power-down n one h x x l x l x x x l-h three-state deselect cycle, power-down n one l l x l l x x x x l-h three-state deselect cycle, power-down n one l x h l l x x x x l-h three-state deselect cycle, power-down n onellxlh lx x xl-hthree-state deselect cycle, power-down n onelxhlh lx x xl-hthree-state snooze mode, power-down none x x x h x x x x x x three-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h three-state write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h three-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h three-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h three-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h three-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h three-state notes: 2. x = ?don't care.? h = logic high, l = logic low. 3. write = l when any one or more byte write enable signals (bw a , bw b , bw c , bw d ) and bwe = l or gw = l. write = h when all byte write enable signals (bw a , bw b , bw c , bw d ), bwe , gw = h. 4. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 5. the sram always initiates a read cycle when adsp asserted, regardless of the state of gw , bwe , or bw [a:d] . writes may occur onl y on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to three-state. oe is a don't care for the remainder of the write cycle. 6. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cyc les. during a read cycle all d ata bits are three-state when oe is inactive or when the device is deselected, and all data bits behave as output when oe is active (low) .
cy7c1347f document #: 38-05213 rev. *d page 7 of 19 write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d partial truth table for read/write [2, 7] function gw bwe bw d bw c bw b bw a read hhxxxx read hlhhhh write byte a ? dq a hlhhhl write byte b ? dq b hlhhlh write bytes b, a h l h h l l write byte c? dq c hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d? dq d hl lhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b hllllh write all bytes hlllll write all bytes lxxxxx notes: 7. table only lists a partial listing of the byte write combinations. any combination of bw [a:d] is valid. appropriate write will be done ba sed on which byte write is active. truth table [2, 3, 4, 5, 6] next cycle add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq
cy7c1347f document #: 38-05213 rev. *d page 8 of 19 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 65 c to +150 c ambient temperature with power applied .................................................. ? 55 c to +125 c supply voltage on v dd relative to gnd .........? 0.5v to +4.6v dc voltage applied to outputs in high-z state ........................................... ? 0.5v to v dd + 0.5v dc input voltage ....................................... ? 0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq com?l 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd ind?l ?40c to +85c electrical characteristics over the operating range [8, 9] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage 2.375 v dd v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ?2.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 2.0 ma 0.7 v v ih input high voltage [8] v ddq = 3.3v 2.0 v dd + 0.3v v v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [8] v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current ex- cept zz and mode gnd v i v ddq ? 5 5 a input current of mode input = v ss ? 30 a input = v ddq 5 a input current of zz input = v ss ? 5 a input = v ddq 30 a i oz output leakage current gnd v i v ddq, output disabled ? 5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 4-ns cycle, 250 mhz 325 ma 4.4-ns cycle, 225 mhz 290 ma 5-ns cycle, 200 mhz 265 ma 6-ns cycle, 166 mhz 240 ma 7.5-ns cycle, 133 mhz 225 ma i sb1 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il f = f max = 1/t cyc 4-ns cycle, 250 mhz 120 ma 4.4-ns cycle, 225 mhz 115 ma 5-ns cycle, 200 mhz 110 ma 6-ns cycle, 166 mhz 100 ma 7.5-ns cycle, 133 mhz 90 ma i sb2 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in 0.3v or v in > v ddq ? 0.3v, f = 0 all speeds 40 ma notes: 8. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > -2v (pulse width less than t cyc /2). 9. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200ms. during this time v ih < v dd and v ddq < v dd
cy7c1347f document #: 38-05213 rev. *d page 9 of 19 i sb3 automatic ce power-down current?cmos inputs max. v dd , device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max = 1/t cyc 4-ns cycle, 250 mhz 105 ma 4.4-ns cycle, 225 mhz 100 ma 5-ns cycle, 200 mhz 95 ma 6-ns cycle, 166 mhz 85 ma 7.5-ns cycle, 133 mhz 75 ma i sb4 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = 0 45 ma shaded areas contain advance information. capacitance [10] parameter description test conditions tqfp package bga package fbga package unit c in input capacitance t a = 25 c, f = 1 mhz, v dd = 3.3v. v ddq = 3.3v 5 5 5 pf c clk clock input capacitance 5 5 5 pf c i/o input/output capacitance 5 7 7 pf ac test loads and waveforms thermal resistance [10] parameter description test conditions tqfp package bga package fbga package unit q ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 41.83 47.63 20.3 c/w q jc thermal resistance (junction to case) 9.99 11.71 4.6 c/w note: 10. tested initially and after any design or proc ess changes that may affect these parameters. electrical characteristics over the operating range (continued) [8, 9] parameter description test conditions min. max. unit output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load 2.5v i/o test load
cy7c1347f document #: 38-05213 rev. *d page 10 of 19 switching characteristics over the operating range [15, 16] parameter description -250 -225 -200 -166 -133 unit min. max. min. max. min. max. min. max. min. max. t power v dd (min.) to the first access read or write [11] 1 1 111 ms t cyc clock cycle time 4.0 4.4 5.0 6.0 7.5 ns t ch clock high 1.7 2.0 2.0 2.5 3.0 ns t cl clock low 1.7 2.0 2.0 2.5 3.0 ns t as address set-up before clk rise 0.8 1.2 1.2 1.5 1.5 ns t ah address hold after clk rise 0.4 0.5 0.5 0.5 0.5 ns t co data output valid after clk rise 2.6 2.6 2.8 3.5 4.0 ns t doh data output hold after clk rise 1.0 1.0 1.0 2.0 2.0 ns t wes gw , bws [3:0] set-up before clk rise 0.8 1.2 1.2 1.5 1.5 ns t weh gw , bws [3:0] hold after clk rise 0.4 0.5 0.5 0.5 0.5 ns t als adv/ld set-up before clk rise 0.8 1.2 1.2 1.5 1.5 ns t alh adv/ld hold after clk rise 0.4 0.5 0.5 0.5 0.5 ns t ds data input set-up before clk rise 0.8 1.2 1.2 1.5 1.5 ns t dh data input hold after clk rise 0.4 0.5 0.5 0.5 0.5 ns t ces chip enable set-up before clk rise 0.8 1.2 1.2 1.5 1.5 ns t ceh chip enable hold after clk rise 0.4 0.5 0.5 0.5 0.5 ns t chz clock to high-z [12, 13, 14] 2.6 2.6 2.8 3.5 4.0 ns t clz clock to low-z [12, 13, 14] 0 0 0 0 0 ns t eohz oe high to output high-z [12, 13, 14] 2.6 2.6 2.8 3.5 4.0 ns t eolz oe low to output low-z [12, 13, 14] 0 0 0 0 0 ns t eov oe low to output valid 2.6 2.6 2.8 3.5 4.5 ns notes: 11. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially before a read or write operation can be initiated. 12. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 13. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention co ndition, but reflect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions. 14. this parameter is sampled and not 100% tested. 15. timing references level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v on all data sheets. 16. test conditions shown in (a) of ac test loads unless otherwise noted.
cy7c1347f document #: 38-05213 rev. *d page 11 of 19 switching waveforms read cycle timing [17] notes: 17. on this diagram when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high,ce 1 is high or ce 2 is low or ce 3 is high. 18. full width write can be initiated by either gw low, or by gw high, bwe low and bw [a:d] low. t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bw [a:d] d ata out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address don?t care undefined
cy7c1347f document #: 38-05213 rev. *d page 12 of 19 write cycle timing [17, 18] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw[a:d] d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3
cy7c1347f document #: 38-05213 rev. *d page 13 of 19 read/write cycle timing [17, 19, 20] note: 19. the data bus (q)remains in high-z following a write cycl e, unless a new read access is initiated by adsp or adsc . 20. gw is high switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces bwe, bw[a:d] d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 don?t care undefined a3
cy7c1347f document #: 38-05213 rev. *d page 14 of 19 notes: 21. device must be deselected when entering zz mode. see cycle descr iptions table for all possible signal conditions to deselect the device. 22. dqs are in high-z when exiting zz sleep mode. switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only zz mode timing [21, 22]
cy7c1347f document #: 38-05213 rev. *d page 15 of 19 ordering information speed (mhz) ordering code package name package type operating range 250 cy7c1347f-250ac a101 100-lead thin quad flat pack commercial cy7c1347f-250bgc bg119 119-ball bga 225 cy7c1347f-225ac a101 100-lead thin quad flat pack commercial cy7c1347f-225bgc bg119 119-ball bga 200 cy7c1347f-200ac a101 100-lead thin quad flat pack commercial cy7c1347f-200bgc bg119 119-ball bga cy7c1347f-200bzc bb165c 165-ball fbga cy7c1347f-200ai a101 100-lead thin quad flat pack industrial cy7c1347f-200bgi bg119 119-ball bga 166 CY7C1347F-166AC a101 100-lead thin quad flat pack commercial cy7c1347f-166bgc bg119 119-ball bga cy7c1347f-166bzc bb165c 165-ball fbga cy7c1347f-166ai a101 100-lead thin quad flat pack industrial cy7c1347f-166bgi bg119 119-ball bga 133 cy7c1347f-133ac a101 100-lead thin quad flat pack commercial cy7c1347f-133bgc bg119 119-ball bga cy7c1347f-133bzc bb165c 165-ball fbga cy7c1347f-133ai a101 100-lead thin quad flat pack industrial cy7c1347f-133bgi bg119 119-ball bga shaded areas contain advance information. please contact your local cypress sales r epresentative for availability of these parts.
cy7c1347f document #: 38-05213 rev. *d page 16 of 19 package diagrams 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
cy7c1347f document #: 38-05213 rev. *d page 17 of 19 package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
cy7c1347f document #: 38-05213 rev. *d page 18 of 19 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. intel and pentium are registered trademarks of intel corporation. powerpc is a registered trademark of international business machines, inc. all product and company names mentioned in this document may be the trademarks of their respective holders. package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05mc b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin1corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 165-ball fbga (15 x 17 x 1.20 mm) bb165c 51-85165-*a
cy7c1347f document #: 38-05213 rev. *d page 19 of 19 document history page document title: cy7c1347f 4-mbit (128k x 36) pipelined sync sram document number: 38-05213 rev. ecn no. issue date orig. of change description of change ** 119829 12/16/02 hgk new data sheet *a 123117 01/18/03 rbi added power-up requirements to ac test loads and waveforms information *b 127632 06/13/03 dpm final data sheet *c 200660 see ecn swi improvements: updated thermal resistance and capacitance updated r5 pin of 119-ball bga from v dd to nc updated all switching waveforms clarifications: updated footnotes updated zz mode electrical characteristics *d 213342 see ecn vbl update ordering info section: delete -100, shade -250, -225 delete -100, shade -250, -225 data fr om selection guide and characteristics

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